The 1964 CDC6600 (fastest supercomputer of the 1960s) would be classified as RISC if made today, as would the Cray 1 (ditto 70s).
Both have a lot of similarities to modern RISC-V, including the use of two instruction lengths (15 and 30 bits on CDC6600, 16 and 32 bits on Cray 1), which both the IBM 801 and RISC-II also did.
The Cray 1's Vector instruction set is also very similar to RISC-V's V extension. The biggest difference is on the Cray 1 the programmer has to know the vector registers are 64 elements long and set the correct length (1-64 elements) using the "0020xk Transmit (Ak) to VL" instruction on each iteration of the strip-mining loop. On RISC-V you tell "vsetvl" how many elements remain in your vector and the instruction returns as its result how many elements it can process, so RISC-V CPUs can have wildly different vector register lengths but run the same code.
"The other major change was to include an instruction-format expander, which invisibly "up-converted" 16-bit instructions into a 32-bit format. This allowed smaller instructions, typically things with one or no operands, like NOP, to be stored in memory in a smaller 16-bit format, and for two such instructions to be packed into a single machine word. The instructions would be invisibly expanded back to 32-bit versions before they reached the arithmetic logic unit (ALU), meaning that no changes were needed in the core logic. This simple technique yielded a surprising 30% improvement in code density, making an otherwise identical program on Blue run faster than on Gold due to the decreased number of memory accesses."
Not yet visible to the average consumer, but it is hardware and hardware projects take pretty much 5 years to go from green light to products in stores. There is a LOT in the pipeline ... projects, products, startups.
Note that the forever "no incompatible changes" RISC-V base user mode and privileged ISA pretty much started with the publication of Priv arch 1.10 in May 2018, less than six years ago. It was ratified as 1.11 (mostly just documentation improvements, and minor tweaks) in July 2019, less than four years ago. The User mode ISA was stable already in 2015.
Essentially July 2019 was the starting gun.
RISC-V cores announced in late 2018 (SiFive U74) and mid 2019 (Alibaba THead C910) are just now making it into mass-production products at affordable prices, such as the VisionFive 2, Star64 and PineTab-V, Lichee Pi 4A.
That's just normal hardware time scales.
There is a flood of products in progress now and coming out over the next 3-5 years, by which time RISC-V products will be at least matching today's Intel / AMD / Apple performance levels. Those companies will have moved on by then, of course, but probably not far.
It's worth noting that at the time memory bandwidth was underutilised and the bottleneck was execution, hence lower instruction density was acceptable. The RISC concept is now applicable in the form of uops.
Intel's disinformation campaign's[0] damage is yet to be undone.
I have come to understand and accepted that every post about RISC will get some replies containing claims, equally wild as they are wrong, about uops being RISC, or otherwise making RISC redundant.
Is "disinformation campaign" the most FUD you can come up with? Where's your actual counterargument then?
ARM breaks down instructions into uops too.
Pure RISC was never good. Look at how ARM and x86 are very closely matched in efficiency in these studies, but MIPS (which is what RISC-V is quite similar to) is noticeably far behind:
All of SiFive's designs offer better performance, power and area than ARM's equivalent offerings.
>ARM breaks down instructions into uops too.
Most large implementations do today, irrespective of ISA.
>Look at how ARM and x86 are very closely matched in efficiency in these studies, but MIPS (which is what RISC-V is quite similar to) is noticeably far behind
MIPS had poor code density. x86 and thumb2 had good code density. amd64 (x86-64) code density degraded relative to x86, due to adding new prefix for the 64bit instructions.
aarch64 degraded relative to thumb2, due to fixed instruction length. RISC-V has variable instruction length designed to avoid decoder complexity.
RISC-V already has the best code density among all 64bit ISAs. It has the best code density among all 32bit ISAs too, with the draft code size extensions.
Ascalon[0][1] expects performance competitive with Zen5, at lower power consumption. Both will be available in 2024.
Tenstorrent's is just one of the known very high performance targeting cores under development. Others include Ventana (first chip TBA late 2023), Rivos and MIPS.
The 1964 CDC6600 (fastest supercomputer of the 1960s) would be classified as RISC if made today, as would the Cray 1 (ditto 70s).
Both have a lot of similarities to modern RISC-V, including the use of two instruction lengths (15 and 30 bits on CDC6600, 16 and 32 bits on Cray 1), which both the IBM 801 and RISC-II also did.
The Cray 1's Vector instruction set is also very similar to RISC-V's V extension. The biggest difference is on the Cray 1 the programmer has to know the vector registers are 64 elements long and set the correct length (1-64 elements) using the "0020xk Transmit (Ak) to VL" instruction on each iteration of the strip-mining loop. On RISC-V you tell "vsetvl" how many elements remain in your vector and the instruction returns as its result how many elements it can process, so RISC-V CPUs can have wildly different vector register lengths but run the same code.